Introduction to LEON for UT SoC

INTRODUCTION

LEON is a 32-bit processor conforming to the IEEE-1754(SPARC V8) standard. The VHDL model of the processor, which is available free, and is highly flexible can be configured and made suitable for embedded applications and system-on-chip (SoC) designs.

LEON was initially developed to at European Space Agency (ESA) by Jiri Gaisler to be used in space missions. To promote the SPARC standard and enable development of system-on-a-chip (SOC) devices using SPARC cores, the ESA is making the source code freely available under the GNU LGPL license. The first public LEON release was LEON-1.0 in October 1999. The work on LEON started in 1997, and took 2 years to complete the first release of the design. AMBA buses were added in October 2000. The first LEON on silicon was fabbed in beginning of 2001 (Atmel 0.35 um). Leon2 with the DSU was released in February 2002. However Jiri Gaisler left the agency in January 2001 and found Gaisler Research which provides simulators, compilation tools and boards for development of LEON and ERC32 processor cores.

LEON Architecture Overview

The LEON processor is designed for embedded applications containing the following on-chip features:

Separate instruction and data cache (Harvard Architecture)
Hardware Multiplier and Divider
Interrupt controller
Debug Support Unit with trace buffer
Two 24-bit timers
Two UARTs
16-bit I/O port and a flexible memory controller.
Full implementation of AMBA AHB/APB buses.

Figure: LEON Architecture Block Diagram

Details of the architecture can be obtained from the LEON documentation.

Configuring LEON for A Specific Application

The leon2-1.0.10 tar ball can be downloaded from here. The configuration of the VHDL model can be done initially using the GUI provided with the LEON release.

LEON Configuration for UT SoC

For our project we selected the target technology in the synthesis tab as Xilinx Virtex, and in memory select 'no' for the 8-bit memory bus support since we are going to use 32-bit bus. We did not select the co-processor, floating point unit, PCI and retained the default values for the rest of the bullets. Boot option is external memory. We then save our configuration and at the command prompt type "make dep". This command writes the "device.vhd" based on the configurations chosen. We also generated the files for ASIC, targeting TSMC 0.25 um technology.

The VHDL model available is synthesizable with most of the synthesis tools and can be implemented on both FPGAs and ASICs. The LEON version used by us in this project is leon2-1.0.10. The only technology-specific mega-cells needed are RAM cells for caches and register file.

Synthesis and Simulation

The LEON downloads from Gaisler Research provide scripts for synthesis with Synopsys synthesis tools (FPGA Compiler II and Design Compiler), Synplicity's Synplify, Exemplar Leonardo and Xilinx Synthesis Tools. Generic test benches have also been provided which can be used for pre- and post-synthesis simulation on the netlist. We first tested the LEON, stand-alone, then added an APB slave and tested the design using a modified test-bench.