Post Layout Simulation

We have used spectre to simulate the schematic before, but the layout is different from schematic in the sense that some parasitic capacitance and resistance information cannot be obtained in the schematic. For example, the schmatic editor cannot determine the wire capacitance and resistance information because schematic only worries about netlist and they do not have the wiring information (i.e. how the wire is routed). Because of this, it is very important to perform a post-layout simulation from the extracted view since it is closer to the reality. 

In the Extracted layout window, click on Tools -> Simulation -> Spectre to invoke spectre. Follow the steps in circuit simulation with Spectre to simulate the circuit. 

This simulation should be used to determine the final circuit behavior. If the timing of the circuit doesnot satisfy the timing requirement. We will have to modify the layout or even the schematic to adjust the size of the transistor and wire or even reconstruct the logic until the constraint is finally satisfied.