Cadence Tutorial of UTK

The objective of this home page is to give a tutorial to circuit designers who would like to get acquainted with Cadence design tools.  A step by step tutorial approach is adopted.  It is the hope of the author that by the end of this tutuorial session, the user would have known how to create a schematic, perform simple manual layouts and, of course, run simulations (Pre-Spectre & post layout).

Those of you who have some basic knowledge of Cadence tools already may prefer to jump ahead to your desired topic without fearing the loss of continuity.  Some topics might appear tedious, but be patient... there's light at the end of the tunnel.

The setup is for the environment of the Department of Electrical and Computer Engineering, University of Tennessee, Knoxville. Outside users need to modify some setups for their own environments. Please click on the links to get a detailed description:
 

• Setting up the Cadence environment
• Library Manager
• Schematic Composer
• Create Symbols
• Simulation with Verilog-XL
• Circuit simulation with Spectre
• Custom Layout with Virtuoso
• Layout extraction and Layout Versus Schematic (LVS) with Diva
• Post Layout Simulation