Cadence Tutorial of UTK

Simulation with Verilog-XL


We use Verilog-XL to simulate our designs at logic level. In another word, we can only check if our design if functionally correct by using Verilog simulation. We will not be able to know, for example, the transient behavior of the circuit. Thus we will not be able to know the delay and timing information for the circuit. To simulate the transient behavior, we should use Cadence SPECTRE which is very similar to SPICE. 

Still, Verilog simulation is very important. A circuit has to be verified to be functionally correct before we look into its transient behavior. This section talks about how to write a Verilog "testbench" for the schematic we created and simulate its behavior. In order to use this tool, only minimal knowledge of Verilog is required (basically on how to supply the stimuli during the simulation).
 

  • Start Verilog-XL

    • In the schematic design window, click on Tools-> Simulation->Verilog-XL to start the verilog-XL. A pop up dialogue box will appear. 
     
     

    Use the default settings would create a directory named inverter.run1 under the cadence run directory for the verilog simulation. We can specify another path if needed. In this case, we use the default settings. Now a Verilog simulation window appears.
     

  • Create stimulus file 

    • Now in this Verilog simulation window, click on Stimulus->Verilog..., a pop up message box appears.
     
     

    For the first run, since we do not have a stimulus file yet, we click on Yes. A template file named testfixture.verilog has been created for us and a new pop up window appears.
     
     

    Choose testfixture.verilog as our stimulus file. Now we can modify this file to supply the stimuli during the simulation. Use any text editor to edit this file under the simulation directory (~/run/inverter.run1/testfixture.verilog in this example). The orginal file is shown in the left window below. Now we create a square wave for the input by letting inv_in to be "1" at 100ns and "0" again at 200ns. The modified simulation file is shown in the right window below.

  • Simulate Before we start simulation, we should record all the signals that we want to display later. Click on Setup->Record Signals and record All signals in the simulation window so that we can record all the signals during the simulation to help debug our designs.

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    Now click on Simulation->Start Interactive in the simulation window. The simulation initiates. Click on Simulation->Continue to complete simulation. The simulation window looks like below when it completes.

    If we run into any problem in the simulation, we can check on the si.log in the simulation directory (~/run/inverter.run1 in this example.)
     

  • View Waveforms

    • We can use a tool called "Signalscan" to view the results in a waveform format. Click on Debug->Utilities->View Waveform in the simulation window. The waveform window appears.

    In the waveform tool window, click on Windows->Design Browser, a design browser window pops up. Click on test in the Instances in current context window. Select all the signals interested (in this example both inv_in and inv_out) by clicking on them in the Nodes/Variables in Current Context window. Finally Click on "AddToWaves" button to display the waveforms in the waveform window.