Protected Website for ECE 651



ECE 651



01-SJSU-Cadence Website (html)

02-SJSU-Learning Unix (43-page pdf)

03-SJSU-Cadence Tutorial icfb (98-page pdf)

04-SJSU-Designing with IIT Cells (32-page pdf)

05-IIT-VLSI Tools and Cells (html)

06-IIT-Standard Cell Library (4-page pdf)

07-SJSU-Project Presentation PPT Template (11-slides ppt)

08-SJSU-Project Report (98-page pdf)

09-std-cell-lef (html)

10-std-cells-figs (html)

11-std-cell-examples (html)

12-spectre-user (343-page pdf)

13-hspice-ref (96-page pdf)

14-JSSC-Most Cited Papers (html)

15-ASIC Trends

16-Rapidchip Market (16 Kbytes pdf) 17-Rapidchip Overview (81 KBytes pdf) 18-Rapidchip Tutorial (818 KBytes pdf)

19-tsmc-fab-jun04.pdf

20-design-for-yield-and-structured-asics.pdf

21-News items of interest -- Nov 03 (txt)

22-Cost-Performance Per Watt

23-Kang-Chapter1-slides (pdf)

24-Kang-Chapter2-slides (pdf)

25-Kang-Chapter5-slides (pdf)

26-Patel-ProGenesis-slides-notes (pdf)

27-Tanner AMI-0.5um Standard Cell Library (pdf)

28-Smoking CPUs

29-Itanium2 (pdf)

30-OpenCourseWare at MIT

31-MIT Low Power Slides (pdf)

32-UMich Razor (pdf)

33-Intel CPU

34-Datapath Example

35-Standard Cell Example

36-Placement and Routing

37-Career Services

38-Mixed-Signal IC Layout

39-Pads for AMI-0.6 process (pdf)

40-Guard Rings (gif)

41-ICCAD Tutorial on Physical Design

42-Slides from Univ. of Utah

43-Cadence for CMU Juniors

44-Embedded RAM

45-Analog VLSI Design Resource Kit

46-Dr. Blalock's Guest Lecture Slides (pdf)

47-Switched Capacitor Filters

48-How Chips are Made

49-How Transistors Work

50-How Microprocessors Work

51-Die Photo of Intel Pentium

52-Die Photo of SUN Ultrasparc

53-Die Photo of DEC Alpha 21164

54-ORNL Nanoscale Science Lab (clean room)

55-MSU LEF slides (pdf)

56-Old ECE 651 Projects

57-Cells for 180-nm process

58-Intel 4004 Schematics

59-Crafting-A-Chip: Ch. 1 -- Introduction (6 pages--pdf)

60-Crafting-A-Chip: Ch. 2 -- Cadence icfb (8 pages--pdf)

61-Crafting-A-Chip: Ch. 3 -- Composer Schematic Capture (22 pages--pdf)

62-Crafting-A-Chip: Ch. 4 -- Verilog Simulation (68 pages--pdf)

63-Crafting-A-Chip: Ch. 5 -- Virtuoso Layout Editor (52 pages--pdf)

64-Crafting-A-Chip: Ch. 6 -- Spectre Analog Simulation (38 pages--pdf)

65-Crafting-A-Chip: Ch. 7 -- Cell Characterization (40 pages--pdf)

66-Crafting-A-Chip: Ch. 8 -- Verilog Synthesis (33 pages--pdf)

67-Crafting-A-Chip: Ch. 9 -- Abstract Generation (12 pages--pdf)

68-Crafting-A-Chip: Ch.10 -- SOC Encounter Place and Route (48 pages--pdf)

69-Crafting-A-Chip: Ch.11 -- Chip Assembly (34 pages--pdf)

70-ST & IBM 32-nm CMOS

71-Overview Slides Part 2 (pdf)

72-MOS-Opamp-Design (pdf)

73-OSU AMI06 (html)

74-TSMC018 (html)

75-Beyond Moore's Law (pdf) [IEEE Spectrum, Oct. 2007]

76-Intel 45nm Photos (html)

77-Cadabra-product (html)

78-Cadabra-paper (pdf)

79-Cadabra-presentation (pdf)

80-Intel-22nm-3d (pdf)


dbouldin@utk.edu