The above block diagram shows the entire system. The data from other blocks in the SoC is written into the input RAM via the input RAM data write bus and the input ram write address bus. When all the data to be encrypted is written into the RAM the 'go' signal is made high. The controller block of the system takes over the control and transfers the data to the DES block where the encryption begins. The output of the DES which is the ciphered text is read and written into the output RAM by the controller. This can be read but other blocks of the SoC via the output ram read bus.

This block was simulated and these are the screenshots.

Screenshot1 This shows the first set of key and plain text (pt) LSB and MSB being read from the input RAM.

Screenshot2 This shows the calculated ciphertext (ct) for the first set of data being written to the output RAM.

Screenshot3 This shows the second set of key and plain text (pt) LSB and MSB being read from the input RAM.

Screenshot4 This shows the calculated ciphertext (ct) for the second set of data being written to the output RAM.

Screenshot5 This shows the stored ciphertext being read from the output RAM .

First set of data: Key: 0123456789abcdef (hex) Plaintext: 1111111111111111 (hex)

Expected ciphered text output:17668dfc7292532d(hex)

Second set of data: Key: 0101010101010101 (hex) Plaintext: 0123456789abcdef (hex)

Expected ciphered text output: 617b3a0ce8f07100 (hex)

The pre layout simulation results match the expected results.

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