Design compiler |
Design compiler is used to synthesize the DES module to get the gate-level
netlist.The two important blocks inside the DES is |
Key Scheduler |
Round
Function |
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Design Elaborator |
The following figure shows the output of Design Elaborator |
![](design_elaborate.gif)
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Top
Module |
The following figure shows the Overall schematic of the Topmodule |
![](schematic.gif)
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The following figure shows the Symbolic view of the overall topmodule of DES |
![](symbol.gif)
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Key
Scheduler |
The following figure shows the Schematic view of the Key Scheduler of DES |
![](keyschematic.gif)
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The following figure shows the Symbolic view of the Key Scheduler of DES . |
![](keysymbol.gif)
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The following figure shows the Hierarchical view of the Key Scheduler of DES . |
![](keyhierarchy.gif)
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Round
Function |
The following figure shows the Schematic view of the Round Function of DES . |
![](roundschematic.gif)
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The following figure shows the Symbolic view of the Round Functionof DES . |
![](roundsymbol.gif)
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The following figure shows the Hierarchical view of the Round Function of DES . |
![](roundhierarchy.gif)
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Critical path |
The following figure shows the critical path in the DES module. |
![](criticalpath.gif)
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Layout |
The following figure shows the Silicon ensemble layout of the DES module. |
![](siliconensemble.gif)
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The following is the floorplan
report from Silicon ensemble |
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The following figure shows the Final layout. |
![](finallayout.gif)
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The following figure shows the Zoomed view. |
![](ash.gif)
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The following figure shows the Extracted view . |
![](extracted.gif)
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The following figure shows the Log window of Extraction. |
![](log.gif)
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The following figure shows the LVS check between the Schematic and Extracted view. |
![](lvs.gif)
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Gate-Level back-annotation Simulation |
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Once the Layout has been performed , an sdf file corresponding to DES is exported from silicon ensemble.
The sdf file and the gate-level netlist are used to do the Post-synthesis simulation |
The following figure shows the Post-layout verification window. |
![](postlayout.gif)
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The
following figure shows the Post-layout Simulation of DES. |
![](postlayoutsimulation.gif)
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Schematic from Netlist |
The Gate-level netlist generated from Design Compiler can be used to get the Schematic
of the DES module.The netlist has to be imported into ICFB to get the Schematic. |
The following figure shows the Schematic of the Top module of DES. |
![](topschematic.gif)
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The following figure shows the Zoomed Schematic view of the Top module of DES. |
![](schematiczoom.gif)
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The following figure shows the Symbol of the Top module of DES. |
![](topsymbol.gif)
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The following figure shows the Schematic view of Key Scheduler of DES. |
![](keyschedschematic.gif)
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The following figure shows the Zoomed Schematic of the Key Scheduler of
DES |
![](gkeyschedschematiczoom.gif)
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The following figure shows the Symbolic view of the Key Scheduler of DES. |
![](keyschedsymbol.gif)
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The following figure shows the Schematic view of the Round Function of DES. |
![](roundfunctionschematic.gif)
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The following figure shows the Zoomed Symbolic view of the Round Function of DES. |
![](roundfunctionschematiczoom.gif)
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The following figure shows the Symbolic view of the Round Function of DES. |
![](roundfunctionsymbol.gif)
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