RAM
| The following screenshot show the Post Layout Simulation of the RAM Block |
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| Using DC Compiler |
| The following figure shows the schematic view of the Designware RAM used in the project. |
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| The following figure shows the Symbolic view |
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| Schematic from Netlist |
| The gate-level netlist of RAM was used to get the schematic using ICFB |
| The following figure shows the Schematic of the RAM |
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| The following figure shows the symbolic view |
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