Summary  
 
The Post Synthesis simulation was performed using the sdf (standard delay format) file obtained after place and route. It matched with the expected results. The following Screenshot shows the Pre Layout versus Post Layout Simulation. This was done to make sure that the input data was being written to the Input RAM, the DES used the data to perform encryption and the result was stored back to the Output RAM. The following figure gives the summary of tools used in this project.

Figure: List of Tools used in our project

 
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DES on Xilinx

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