DES
| Targeting DES to FPGA |
| The DES module is targeted to Xilinx's
virtex 1000e.
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| Result of FPGA compiler |
| Synopsys's FPGA compiler is used to synthesize the DES module in order to target to the Xilinx' Chip. |
| The following figure shows the View of DES obtained using FPGA compiler. |
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| The following figure shows the zoomed view. |
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| The following is the result obtained using the FPGA compiler |
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| Place and Route |
| Xilinx Place and Route program was used to map the DES design in the chip followed by Placing and Routing . |
| The following figure shows the Place and Route results. |
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| The following figure shows the Layout. |
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| DES interfaced with Xilinx's coregen |
| The idea here is to have one dual-port RAM and the DES module gets its values from it. Once the DES module calculates the ciphered text , it would be put back into to same RAM. The following figure shows the compile log of pre-layout simulation |
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| The following figures shows the Pre-layout simulation |
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| Synthesis Results |
| FPGA compiler was used to synthesize the entire block. The following is the synthesis result |
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| The following is the mapping result |
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| The following shows the layout of the entire block (DES+xilinx coregen) on the Virtex 1000E |
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| DES interfaced with Synopsys' Designware RAM |
| Mapping of the Entire DES with the Designware RAM was done on Xilinx's virtex 1000E. |
| The following is the Synthesis results |
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| The following is the mapping results |
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| The following is the layout |
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