Garrett S. Rose
Neuromorphic Computing Hardware Design (Project Site)

A "natural" candidate for emerging computer architectures is the concept of neuromorphic systems or computational networks constructed from neural networks. Neuromorphic computer architectures are inspired by biology in that their operation is based on our best understanding of the functionality of the mammalian brain. While artificial neural networks can be constructed from conventional electronic devices such as transistors, emerging nanoscale devices (e.g. memristors) exhibit properties particularly well suited for building high density, power-efficient neuromorphic systems. As part of our research, we are exploring how memristive devices can be exploited as synaptic elements in complex neural networks. This approach of "memristors as synapses" has been applied to several neuromorphic architectures, including brain-state-in-a-box (BSB) and popular Hopfield networks. Furthermore, in contrast to most silicon based reconfigurable devices, neuromorphic systems learn or are trained in much the same way as animals must learn. To this end, we are also engaged in the exploration of training methods for the memristor-based neuromorphic systems we design.

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For more information regarding neuromorphic research at UTK: neuromorphic.eecs.utk.edu

Nano-enabled Hardware Security

As is the case with any modern computing system, nanoelectronic architectures must be designed and implemented with special attention paid to potential security concerns. For example, a hardware encryption engine can be designed to provide high security encryption but if not implemented properly information leakage via side-channels (e.g. power) can be exploited by malicious parties to retrieve sensitive information. Side-channel attacks have emerged as a serious concern for computer systems and even strong encryption techniques such as AES can be susceptible to leaky side-channels if the overall system is not designed properly. Recent work in this area includes the design and simulation of a memristor-based system that minimizes the likelihood of a side-channel attack by leveraging the reconfigurability and inherent process variations of memristors.

Hardware security is also concerned with issues such as counterfeiting and design piracy where malicious parties could enter the supply chain for integrated circuits. One popular solution explored by many research groups for combating hardware security concerns is the use of a physical unclonable function (PUF) that can provide unique "fingerprints" for integrated circuits or be used to generate secret keys. A PUF leverages the inherent process variations of an integrated circuit (typically bad news) to generate digital responses that are unique to a particular device implementation. Nanoelectronic PUF circuits have been designed that leverage process variations in properties such as the write-time of memristive devices. More specifically, when driving a write pulse across several memristors simultaneously we have shown that some of the devices will switch and some will not. A unique PUF response can then be generated based on which memristive devices switch. The construction of hardware security primitives from nanoscale devices such as memristors is expected to lead to secure hardware with a small footprint and low power consumption.

XBarPUF
Example of a memristive crossbar-based physical unclonable function (PUF).

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Memristor Device Modeling and Simulation

Designing and simulating nanelectronic circuits built from novel devices requires accurate models that reflects the expected behavior of those devices. As the nanelectronic devices we explore tend to be experimental, industry tested device models do not typically exist. Thus, device models must be developed based on our best understanding of device behavior. Several memristor device models have actually been developed and presented in scientific literature from which one can begin when designing memristor-based circuits. However, memristors, like most nanoelectronic devices, are still experimental such that the models require regular refinement.

Memristor
The memristor as the fourth fundamental circuit element.

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Nanoelectronic Circuit Design for Emerging Computing Architectures

The field of nanoelectronics is often defined as being concerned with any technology whose feature sizes are on the order of just a few nanometers (1×10-9 meters). Many in the field have performed experiments that have shown how such devices could be fabricated with useful properties such as recitification, hysteresis, and negative differential resistance (NDR). Our work in this regard focuses on the uses of such novel devices for the implementation of computer architectures whose behavior often deviates from that of traditional designs. In the past this has even included exploring ways to building computers from organic molecules. To date, our research has led to low-level design techniques for implementing nanoscale electronic circuits. Our circuit-level approach (taking actual experimental data to build up device models) has led to molecular electronic programmable logic circuits, neuromorphic systems and nanoelectronic hardware security primitives. By leveraging the often exotic behavior of nanoelectronic devices this research aims to develop new computer architectures that are smaller, more cost effective and less power hungry as compared to traditional systems.

Goto Pair PMLA
Example of a nanoelectronic architecture: the programmable majority logic array (right) built from NDR-based Goto pair circuits (top-left).

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