Patents
  1. Q. Wu, R. Linderman, G. Rose, H. Li, Y. Chen, and M. Hu, “Method and Apparatus for Performing Close-Loop Programming of Resistive Memory Devices in Crossbar Array based Hardware Circuits and Systems,” U.S. Patent Application Number 14/328,043, filed July 10, 2014.
  2. G. S. Rose, N. McDonald, L.-K. Yan, and B. Wysocki, “Write-Time Based Memristive Physical Unclonable Function,” U.S. Patent Application Number 13/868,529, filed September 18, 2014.
  3. R. Linderman, Q. Wu, G. Rose, H. Li, Y. Chen, and M. Hu, “Apparatus for Performing Matrix-Vector Multiplication Approximation Using Crossbar Arrays of Resistive Memory Devices,” U.S. Patent Application Number 13/965,495, filed August 13, 2013. Patent granted October 6, 2015, U.S. Patent Number US 9152827 B2.
  4. G. S. Rose, R. Pino, and Q. Wu, “Electronic Charge Sharing CMOS-Memristor Neural Circuit,” U.S. Patent Application Number 13/506,856, filed May 15, 2012. Patent granted September 9, 2014, U.S. Patent Number US 8832009 B2.

Book Chapters
  1. B. Wysocki, N. McDonald, C. Thiem, and G. S. Rose, “Hardware-Based Computational Intelligence for Size, Weight, and Power Constrained Environments,” in Network Science and Cybersecurity, R. Pino, Ed., Springer, 2013. (DOI: 10.1007/978-1-4614-7597-2_9)
  2. G. S. Rose, D. Kudithipudi, G. Khedkar, N. McDonald, B. Wysocki, and L.-K. Yan, “Nanoelectronics and Hardware Security,” in Network Science and Cybersecurity, R. Pino, Ed., Springer, 2013. (DOI: 10.1007/978-1-4614-7597-2_7)
  3. D. Kudithipudi, C. Merkel, M. Soltiz, G. S. Rose, and R. E. Pino, “Design of Neuromorphic Architectures with Memristors,” in Network Science and Cybersecurity, R. Pino, Ed., Springer, 2013. (DOI: 10.1007/978-1-4614-7597-2_6)
  4. G. S. Rose and H. Manem, “A Hybrid CMOS-Nano FPGA Based on Majority Logic: From Devices to Architectures,” in CMOS Processors and Memories, Springer Series: Analog Circuits and Signal Processing, K. Iniewski, Ed., Springer, 2010. (DOI: 10.1007/978-90-481-9216-8)
  5. M. R. Stan, G. S. Rose, and M. M. Ziegler, “Hybrid CMOS/Molecular Integrated Circuits,” in Moore’s Law: Beyond Planar Silicon CMOS and into the Nano Era, Springer Series in Material Science, vol. 106, H. Huff, Ed., Springer, 2009.
  6. S. Das, C. A. Picconatto, G. S. Rose, M. M. Ziegler, and J. C. Ellenbogen, “System-Level Design and Simulation of Naomemories and Nanoprocessors,” in Nano and Molecular Electronics Handbook, S. Lyshevski, Ed., CRC, May 2007.
  7. S. Das, G. S. Rose, M. M. Ziegler, C. A. Picconatto, and J. C. Ellenbogen, “Architectures and Simulations for Nanoprocessor Systems Integrated on the Molecular Scale,” in Introducing Molecular Electronics, G. Cuniberti, G. Fagas, and K. Richter, Eds. Berlin: Springer, 2005.

Journal Papers
  1. M. Uddin, M.B. Majumder, H. Manem, K. Beckmann, Z. Alamgir, N. Cady, and G.S. Rose, “Design Considerations for Memristive Crossbar Physical Unclonable Functions,” accepted for ACM Journal of Emerging Technologies in Computing Systems, 2017.
  2. M. Uddin, M.B. Majumder, and G.S. Rose, “Robustness Analysis of a Memristive Crossbar PUF Against Modeling Attacks,” IEEE Transactions on Nanotechnology, vol. 16, no. 3, pp. 396—405, May 2017. (DOI: 10.1109/TNANO.2017.2677882)
  3. J. Rajendran, R. Karri, M. Potkonjak, N. McDonald, G. S. Rose, and B. Wysocki, “Nano Meets Security: Exploring Nanoelectronic Devices for Security Applications,” Proceedings of the IEEE, vol. 103, no.5, pp. 829—849, May 2015. (DOI: 10.1109/JPROC.2014.2387353)
  4. J. Rajendran, R. Karri, and G. S. Rose, “Improving Tolerance to Variations in Memristor-based Applications Using Parallel Memristors,” IEEE Transactions on Computers, vol. 64, no. 3, pp. 733—746, March 2015. (DOI: 10.1109/TC.2014.2308189)
  5. J. Rajendran, H. Zhang, C. Zhang, G. S. Rose, Y. Pino, O. Sinanoglu, and R. Karri, “Fault Analysis-based Logic Encryption,” IEEE Transactions on Computers, vol. 64, no. 2, pp. 410—424, February 2015. (DOI: 10.1109/TC.2013.193)
  6. G. Khedkar, D. Kudithipudi, and G. S. Rose, “Power Profile Obfuscation using Nanoscale Memristive Devices to Counter DPA Attacks,” IEEE Transactions on Nanotechnology, vol. 14, no. 1, pp. 26 – 35, January 2015. (DOI: 10.1109/TNANO.2014.2362416)
  7. M. Hu, H. Li, Y. Chen, Q. Wu, G. S. Rose, and R. Linderman, “Memristor Crossbar-Based Neuromorphic Computing System: A Case Study,” IEEE Transactions on Neural Networks and Learning Systems, vol. 25, no. 10, pp. 1864—1878, October 2014. (DOI: 10.1109/TNNLS.2013.2296777)
  8. M. Soltiz, D. Kudithipudi, C. Merkel, G. S. Rose, and R. E. Pino, “Memristor-Based Neural Logic Blocks for Nonlinearly Separable Functions,” IEEE Transactions on Computers, vol. 62, no. 8, pp. 1597—1606, August 2013. (DOI: 10.1109/TC.2013.75)
  9. G. S. Rose, H. Manem, J. Rajendran, R. Karri, and R. Pino, “Leveraging Memristive Systems in the Construction of Digital Logic Circuits,” Proceedings of the IEEE, vol. 100, no. 6, June 2012. (DOI: 10.1109/JPROC.2011.2167489)
  10. H. Manem, J. Rajendran, and G. S. Rose, “Stochastic Gradient Descent Inspired Training Technique for a CMOS/Nano Memristive Trainable Threshold Gate Array,” IEEE Transactions on Circuits and Systems I, vol. 59, no. 5, May 2012. (DOI: 10.1109/TCSI.2012.2190665)
  11. J. Rajendran, H. Manem, R. Karri, and G. S. Rose, “An Energy-Efficient Memristive Threshold Logic Circuit,” IEEE Transactions on Computers, vol. 61, no. 4, Apr. 2012. (DOI: 10.1109/TC.2011.26)
  12. H. Manem, J. Rajendran, and G. S. Rose, “Design Considerations for Multi-Level CMOS/Nano Memristive Memory,” ACM Journal of Emerging Technologies in Computing Systems, vol. 8, no. 1, Feb. 2012. (DOI: 10.1145/2093145.2093151)
  13. A. Zia, S. Kannan, H. J. Chao, and G. S. Rose, “3D NOC for Many-Core Processors,” Microelectronics Journal, vol. 42, no. 12, pp. 1380—1390, Dec. 2011. (DOI: 10.1016/j.mejo.2011.09.013)
  14. B. Gojman, H. Manem, G. S. Rose, and A. DeHon, “Inversion Schemes for Sublithographic Programmable Logic Arrays,” IET Computers & Digital Techniques, vol. 3, no. 6, pp. 625—642, Nov. 2009. (DOI: 10.1049/iet-cdt.2008.0128)
  15. G. S. Rose and M. R. Stan, “A Programmable Majority Logic Array using Molecular Scale Electronics,” IEEE Trans. Circuits Syst. I, vol. 54, no. 11, pp. 2380–2390, Nov. 2007.
  16. S. Das, A. J. Gates, H. A. Abdu, G. S. Rose, C. A. Picconatto and J. C. Ellenbogen, “Designs for Ultra-Tiny, Special-Purpose Nanoelectronic Circuits,” IEEE Trans. Circuits Syst. I, vol. 54, no. 11, pp. 2528–2540, Nov. 2007.
  17. G. S. Rose, Y. Yao, J. M. Tour, A. C. Cabe, N. Gergel-Hackett, N. Majumdar, J. C. Bean, L. R. Harriott, and M. R. Stan, “Designing CMOS/Molecular Memories while Considering Device Parameter Variations,” ACM Journal of Emerging Technologies in Computing Systems, vol. 3, no. 1, April 2007.
  18. G. S. Rose, M. M. Ziegler, and M. R. Stan, “A Large-Signal Universal Device Model for Nanoelectronic Circuit Simulation,” IEEE Transactions on Very Large Scale Integration, vol. 12, no. 11, pp. 1201—1208, Nov. 2004.

Conference Papers
  1. G.S. Rose, M.B. Majumder, and M. Uddin, “Exploiting Memristive Crossbar Memories as Dual-Use Security Primitives in IoT Devices,” to appear in Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Bochum, Germany, July 2017. (special session)
  2. S. Amer, S. Sayyaparaju, K. Beckmann, N.C. Cady, and G.S. Rose, “A Practical Hafnium-Oxide Memristor Model Suitable for Circuit Design and Simulation,” to appear in Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), Baltimore, MD, May 2017.
  3. S. Sayyaparaju, G. Chakma, S. Amer, and G.S. Rose, “Circuit Techniques for Online Learning of Memristive Synapses in CMOS-Memristor Neuromorphic Systems,” to appear in Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI), Banff, Alberta, Canada, May 2017.
  4. W. Olin-Ammentorp, K. Beckmann, J.E. Van Nostrand, G.S. Rose, M.E. Dean, J.S. Plank, G. Chakma, and N.C. Cady, “Applying Memristors Towards Low-Power, Dynamic Learning for Neuromorphic Applications,” in Proceedings of the Government Microcircuit Applications and Critical Technology Conference (GOMACTech), Reno, NV, March 2017.
  5. J.S. Plank, G.S. Rose, M.E. Dean, and C.D. Schuman, “A CAD System for Exploring Neuromorphic Computing with Emerging Technologies,” in Proceedings of the Government Microcircuit Applications and Critical Technology Conference (GOMACTech), Reno, NV, March 2017.
  6. M.B. Majumder, M. Uddin, J. Rajendran, and G.S. Rose, “Sneak Path Enabled Authentication for Memristive Crossbar Memories,” in Proceedings of IEEE Asian Hardware Oriented Security & Trust Symposium (AsianHOST), Jiaoxi, Taiwan, Dec. 2016. (DOI: 10.1109/AsianHOST.2016.7835568)
  7. T. Potok, C.D. Schuman, R. Patton, S. Young, G.S. Rose, F. Spedalieri, K.-T. Yao, and R. Lucas, “A Study of Complex Deep Learning Networks on High Performance, Neuromorphic, and Quantum Computers,” in Workshop on Machine Learning in HPC Environments (MLHPC), Salt Lake City, UT, November 2016. (DOI: 10.1109/MLHPC.2016.009)
  8. C. Schuman, J.D. Birdwell, M. Dean, J. Plank, and G. Rose, “Neuromorphic Computing: A Post-Moore’s Law Complementary Architecture,” in International Workshop on Post-Moore's Era Supercomputing (PMES), Salt Lake City, UT, November 2016.
  9. G. Chakma, M.E. Dean, G.S. Rose, K. Beckman, H. Manem, and N. Cady, “A Hafnium-Oxide Memristive Dynamic Adaptive Neural Network Array,” in International Workshop on Post-Moore's Era Supercomputing (PMES), Salt Lake City, UT, November 2016.
  10. M. Uddin, M.B. Majumder, G.S. Rose, H. Manem, K. Beckmann, Z. Alamgir, and N. Cady, “Techniques for Improved Reliability in Memristive Crossbar PUF Circuits,” in Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Pittsburgh, PA, July 2016. (DOI: 10.1109/ISVLSI.2016.33)
  11. G.S. Rose, M. Uddin, and M.B. Majumder, “A Designer's Rationale for Nanoelectronic Hardware Security Primitives,” in Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Pittsburgh, PA, July 2016. (special session) (DOI: 10.1109/ISVLSI.2016.114)
  12. M.E. Dean, J. Chan, C. Daffron, A. Disney, J Reynolds, J.S. Plank, G.S. Rose, J.D. Birdwell, and C.D. Schuman, “An Application Development Platform for Neuromorphic Computing,” in Proceedings of IEEE International Joint Conference on Neural Networks (IJCNN), Vancouver, Canada, July 2016. (DOI: 10.1109/IJCNN.2016.7727354)
  13. G.S. Rose, “Security Meets Nanoelectronics for Internet of Things Applications,” in Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI), Boston, MA, May 2016. (special session) (DOI: 10.1145/2902961.2903045)
  14. C. Daffron, J. Chan, A. Disney, L. Bechtel, R. Wagner, M.E. Dean, G.S. Rose, J.S. Plank, J.D. Birdwell, and C.D. Schuman, “Extensions and Enhancements for the DANNA Neuromorphic Architecture,” in Proceedings of IEEE SoutheastCon, Norfolk, Virginia, March 2016. (DOI: 10.1109/SECON.2016.7506700)
  15. N.C. Cady, K. Beckmann, H. Manem, M.E. Dean, G.S. Rose, and J.E. Van Nostrand, “Towards Memristive Dynamic Adaptive Neural Network Arrays,” in Proceedings of the Government Microcircuit Applications and Critical Technology Conference (GOMACTech), Orlando, FL, March 2016.
  16. J. Bohl, L.-K. Yan, and G. S. Rose, “A Two-Dimensional Chaotic Logic Gate for Improved Computer Security,” in Proceedings of Midwest Symposium on Circuits and Systems (MWSCAS), Fort Collins, CO, August 2015. (DOI: 10.1109/MWSCAS.2015.7282078)
  17. G. S. Rose and C. A. Meade, “Performance Analysis of a Memristive Crossbar PUF Design,” in Proceedings of Design Automation Conference (DAC), San Francisco, CA, June 2015. (DOI: 10.1145/2744769.2744892)
  18. D. Kudithipudi, C. Merkel, Y. K. Ooi, and G. S. Rose, “On Designing Primitives for Cortical Processors with Memristive Hardware,” in Proceedings of the International IEEE System-on-Chip Conference (SOCC), Las Vegas, NV, September 2014. (DOI: 10.1109/SOCC.2014.6948957)
  19. G. S. Rose, “A Chaos-based Arithmetic Logic Unit and Implications for Obfuscation,” in Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Tampa, FL, July 2014. (DOI: 10.1109/ISVLSI.2014.72)
  20. G. S. Rose, N. McDonald, L.-K. Yan, and B. Wysocki, “A Write-Time Based Memristive PUF for Hardware Security Applications,” in Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, CA, November 2013. (PDF)
  21. G. S. Rose, N. McDonald, L.-K. Yan, B. Wysocki, and K. Xu, “Foundations of Memristor Based PUF Architectures,” in Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), New York, New York, July 2013. (PDF)
  22. M. Hu, H. Li, Q. Wu, G. S. Rose, and Y. Chen, “BSB Training Scheme Implementation on Memristor-Based Circuit,” in Proceedings of the IEEE Symposium on Computational Intelligence for Security and Defence Applications (CISDA), Singapore, April 2013.
  23. M. Hu, H. Li, Q. Wu, G. S. Rose, and Y. Chen, “Training Scheme Analysis for Memristor-Based Neuromorphic Design,” in Proceedings of International Workshop on Neuromorphic and Brain-Based Computing Systems (NeuComp 2013), Grenoble, France, March 2013.
  24. G. S. Rose, J. Rajendran, N. McDonald, R. Karri, M. Potkonjak, and B. T. Wysocki, “Hardware Security Strategies Exploiting Nanoelectronic Circuits,” in Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), Yokohama, Japan, January 2013.
  25. J. Rajendran, G. S. Rose, R. Karri, and M. Potkonjak, “Nano-PPUF: A Memristor-Based Security Primitive,” in Proceedings of the International Symposium on VLSI (ISVLSI), Amherst, Massachussetts, August 2012.
  26. M. Soltiz, C. Merkel, D. Kudithipudi, and G. S. Rose, “RRAM-Based Adaptive Neural Logic Block for Implementing Non-Linearly Separable Functions,” in Proceedings of IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), Amsterdam, Netherlands, July 2012.
  27. M. Hu, H. Li, Q. Wu, and G. S. Rose, “Memristor Crossbar Based Hardware Realization of BSB Recall Function,” in Proceedings of International Joint Conference on Neural Networks (IJCNN), Brisbane, Austrailia, June 2012.
  28. M. Hu, H. Li, Q. Wu, and G. S. Rose, “Hardware Realization of Neuromorphic BSB Model with Memristor Crossbar Network,” in Proceedings of Design Automation Conference (DAC), San Francisco, California, June 2012.
  29. G. S. Rose, R. Pino, and Q. Wu, “A Low-Power Memristive Neuromorphic Circuit Utilizing a Global/Local Training Mechanism,” in Proceedings of International Joint Conference on Neural Networks, San Jose, California, August 2011.
  30. G. S. Rose, R. Pino, and Q. Wu, “Exploiting Memristance for Low-Energy Neuromorphic Computing Hardware,” in Proceedings of IEEE International Symposium on Circuits and Systems, Rio de Janeiro, Brazil, May 2011.
  31. J. Rajendran, R. Karri, and G. S. Rose, “Parallel Memristors Improve Variation Tolerance in Memristive Digital Circuits,” in Proceedings of IEEE International Symposium on Circuits and Systems, Rio de Janeiro, Brazil, May 2011.
  32. H. Manem and G. S. Rose, “A Read-Monitored Write Circuit for 1T1M Memristor Memories,” in Proceedings of IEEE International Symposium on Circuits and Systems, Rio de Janeiro, Brazil, May 2011.
  33. S. Kannan and G. S. Rose, “A Hierarchical 3-D Floorplanning Algorithm for Many-core CMPs,” in Proceedings of IEEE International Symposium on Circuits and Systems, Rio de Janeiro, Brazil, May 2011.
  34. J. Rajendran, H. Manem, R. Karri, and G. S. Rose, “An Approach to Tolerate Variations for Memristor Based Applications,” in Proceedings of International Conference on VLSI Design, Chennai, India, January 2011. (Best Paper Award)
  35. A. Zia, S. Kannan, H. J. Chao, and G. S. Rose, “Highly-Scalable 3D Clos NOC for Many-Core CMPs,” in Proceedings of IEEE International NEWCAS Conference, Montreal, Canada, June 2010.
  36. J. Rajendran, H. Manem, R. Karri, and G. S. Rose, “Memristor Based Programmable Threshold Logic Array,” in IEEE/ACM International Symposium on Nanoscale Architectures, Anaheim, CA, June 2010.
  37. H. Manem and G. S. Rose, “Design Considerations for Variation Tolerant Multilevel CMOS/Nano Memristor Memory,” in Proceedings of the ACM Great Lakes Symposium on VLSI, Providence, Rhode Island, May 2010.
  38. G. S. Rose, “Overview: Memristive Devices, Circuits and Systems,” in Proceedings of the IEEE International Symposium on Circuits and Systems, Paris, France, June 2010. (special session)
  39. X. Guo, S. Lin, W. Refai, and G. S. Rose, "Non-Overlapping Transition Encoding for Global On-Chip Interconnect," in Proceedings of the 2009 IEEE International SOC Conference, Belfast, Northern Ireland, United Kingdom, September 2009.
  40. J. Rajendran, H. Manem, and G. S. Rose, “NDR Based Threshold Logic with Memristive Synapses,” in Proceedings of the IEEE Conference on Nanotechnology, Genoa, Italy, July 2009.
  41. H. Manem and G. S. Rose, “A Crosstalk Minimization technique for Sublithographic Programmable Logic Arrays,” in Proceedings of the IEEE Conference on Nanotechnology, Genoa, Italy, July 2009.
  42. Y. Jiang and G. S. Rose, “A Dual-MOSFET Equivalent Resistor Thermal Sensor,” in Proceedings of the ACM Great Lakes Symposium on VLSI, Boston, Massachusetts, May 2009.
  43. H. Manem and G. S. Rose, “The Effects of Logic Partitioning in a Majority Logic Based CMOS-Nano FPGA,” in Proceedings of the ACM Great Lakes Symposium on VLSI, Boston, Massachusetts, May 2009.
  44. H. Manem and G. S. Rose, “The Effect of Device Parameter Variation on Programmable Majority Logic Arrays,” in Proceedings of the IEEE Conference on Nanotechnology, Arlington, Texas, August 2008.
  45. H. Manem, P. C. Paliwoda, and G. S. Rose, “A Hybrid CMOS/Nano FPGA Architecture built from Programmable Majority Logic Arrays,” in Proceedings of the ACM Great Lakes Symposium on VLSI, Orlando, Florida, May 2008.
  46. P. C. Paliwoda, D. S. Maragal, and G. S. Rose, “Testing Molecular Devices in CMOS/Nano Integrated Circuits,” in Proceedings of the IEEE Conference on Nanotechnology, Hong Kong, China, August 2007, pp. 773-777.
  47. A. C. Cabe, G. S. Rose, and M. R. Stan “Data Encoding Eliminates Parasitic Current Paths in Molecular Memory,” in Proceedings of the IEEE Conference on Nanotechnology, Hong Kong, China, August 2007, pp. 70-75.
  48. N. Gergel-Hackett, G. S. Rose, P. Paliwoda, C. A. Hacker, and C. A. Richter, “On-Chip Characterization of Molecular Electronic Devices: The Design and Simulation of a Hybrid Circuit Based on Experimental Molecular Electronic Device Results,” in Proceedings of the ACM Great Lakes Symposium on VLSI, Stresa, Italy, March 2007.
  49. Z. Qi, W. Huang, A. Cabe, W. Wu, Y. Zhang, G. Rose, and M. R. Stan, “A Design Methodology for a Low-Power, Temperature-Aware SoC Developed for Medical Image Processors,” in Proceedings of the 2006 IEEE International SOC Conference, Austin, TX, September 2006.
  50. A. C. Cabe, Z. Qi, W. Huang, Y. Zhang, M. R. Stan, and G. S. Rose, “A Flexible, Technology Adaptive Memory Generation Tool,” in CDNLive! Silicon Valley 2006 Conference Proceedings, San Jose, CA, September 2006.
  51. G. S. Rose, A. C. Cabe, N. Gergel-Hackett, N. Majumdar, M. R. Stan, J. C. Bean, L. R. Harriott, Y. Yao, and J. M. Tour, "Design Approaches for Hybrid CMOS/Molecular Memory Based on Experimental Device Data," in Proceedings of the ACM Great Lakes Symposium on VLSI, Philadelphia, PA, May 2006, pp. 2-7. (Best Paper Award)
  52. M. R. Stan, G. S. Rose, and M. M. Ziegler, “Hybrid CMOS/molecular Electronic Circuits,” in Proceedings of the International Conference on VLSI Design, Hyderabad, India, Jan. 2006.
  53. G. S. Rose and M. R. Stan, “Memory Arrays Based on Molecular RTD Devices,” in Proceedings of the 3rd IEEE Conference on Nanotechnology, San Francisco, CA, August 2003.
  54. M. M. Ziegler, G. S. Rose, and M. R. Stan, “A Universal Device Model for Nanoelectronic Circuit Simulation,” in Proceedings of the 2nd IEEE Conference on Nanotechnology, Washington, D.C., August 2002, pp. 83–88.