Session | Date | Topic |
---|---|---|
01 | 08/18/Thu | Course Overview; Microelectronic Systems Design |
02 | 08/23/Tue | HW1; Remote Access; Role of Synthesis |
03 | 08/25/Thu | HDL Examples; HW2 (GUI and CLI) |
04 | 08/30/Tue | VHDL for Combinational Logic |
05 | 09/01/Thu | VHDL for Controllers |
06 | 09/06/Tue | Structural VHDL |
07 | 09/09/Thu | Design Methodology; HW3 |
08 | 09/13/Tue | Creating & Integrating IP Blocks |
09 | 09/15/Thu | Validation and Verification |
10 | 09/20/Tue | Asserts; Quality IP Blocks |
11 | 09/22/Thu | Global Design |
12 | 09/27/Tue | No Class (miss# 1) |
-- | 09/29/Thu | No Class (Fall Break) |
13 | 10/04/Tue | Animating Logic Simulations; HW4 |
14 | 10/06/Thu | HDL2Graphics; Graphics2HDL; HW5; Testbenches; HW6B; HW6B-Solution |
15 | 10/11/Tue | Project Descriptions and Assignments |
16 | 10/13/Thu | FPGA Floorplans & Interconnect |
17 | 10/18/Tue | Retargeting & Migration; HW6A |
18 | 10/20/Thu | Reconfigurable Computing |
19 | 10/25/Tue | Keyboard & VGA; Pong; Inferring RAM (p372); CoreGen; DPRAM; BRAM-Gen |
20 | 10/27/Thu | Model-Based Design; HW7 |
21 | 11/01/Tue | VHDL-Verilog Examples; Doug Smith |
22 | 11/03/Thu | SOPC; Xilinx-ARM; Platform Design |
23 | 11/08/Tue | Need for Test; Designing Testable ICs |
24 | 11/10/Thu | Failure Analysis; PRBS/LFSR |
25 | 11/15/Tue | BIST; Boundary Scan |
26 | 11/17/Thu | FPGA Optimizations |
27 | 11/22/Tue | No Class (miss# 2) |
-- | 11/24/Thu | No Class (Thanksgiving) |
28 | 11/29/Tue | Team Presentations; Project Checkoffs |
29 | 12/01/Thu | HW & Reports due at noon |
30 | 12/08/Thu | Final Exam (2:45-4:45 p.m.) [12/5/Mon-12:30-2:30 pm] |