| Session | Date | Topic |
|---|---|---|
| 01 | 08/18/Thu | Introduction to VLSI Systems; Moore's Law (2011) |
| 02 | 08/23/Tue | HW1; CMOS Modeling; Harris#0; Harris#24 |
| 03 | 08/25/Thu | Basic Logic Circuits; Harris#3 |
| 04 | 08/30/Tue | Custom Layout; HW2 |
| 05 | 09/01/Thu | Leaf Cell Design Flow |
| 06 | 09/06/Tue | Pre-Layout & Post-Layout Simulation; Harris#8 |
| 07 | 09/08/Thu | Rules for Datapath Cells; HW3 |
| 08 | 09/13/Tue | Loading and Wiring Delays; Harris#5; Harris#6 HW4 |
| 09 | 09/15/Thu | Rules for Standard-height Cells; HW5 |
| 10 | 09/20/Tue | P&R; Soft Macros; Cell Characterization; HW6 |
| 11 | 09/22/Thu | Leafcell Generators; HW8 |
| 12 | 09/27/Tue | No Class (miss# 1) |
| -- | 09/29/Thu | No Class (Fall Break) |
| 13 | 10/04/Tue | Place & Route |
| 14 | 10/06/Thu | Physical Synthesis |
| 15 | 10/11/Tue | IP Patents; Patent Search |
| 16 | 10/13/Thu | Domino Logic; Harris#10; Metastability |
| 17 | 10/18/Tue | Staged Driving; Harris#6; Clock Tree Synthesis; clock-tree; HW9 |
| 18 | 10/20/Thu | Using Nanosim; HW10 |
| 19 | 10/25/Tue | Latchup and ESD |
| 20 | 10/27/Thu | Analog Kit; Switched-Capacitor Circuits; Filters |
| 21 | 11/01/Tue | Static Timing Analysis; Signal Integrity; HW11 |
| 22 | 11/03/Thu | Analog Design; Analog Issues; HW7 |
| 23 | 11/08/Tue | SystemC; SystemC Tutorial; SystemVerilog; Constrained-Random |
| 24 | 11/10/Thu | SeamlessCVE; Platform Express; Px; Trusted ICs; Kill Switch |
| 25 | 11/15/Tue | IC Careers; Carson Fischer; HK-MG; Tri-Gate; More-than-Moore; CMP; 45-nm fab |
| 26 | 11/17/Thu | Chartered; Global Foundries; ITRS; Variability; DFY; RAZOR; 50-core IC |
| 27 | 11/22/Tue | No Class (miss# 2) |
| -- | 11/24/Thu | No Class (Thanksgiving) |
| 28 | 11/29/Tue | No Class (miss# 3); All Homework Due 12/1/Thu-noon |
| 29 | 12/08/Thu | Final Exam (2:45-4:45 p.m.) |
