ECE 651 -- Computer-Aided Design of VLSI Systems I



ECE 651 (Section# 48040) meets Tues/Thurs 2:10-3:25 p.m. in 510 Ferris Hall
Fall 2011

Note: You may register on-line without taking ECE 551 or ECE 552 by contacting
Julia Elkins at (jelkins@utk.edu) to obtain "override" permission.

Don Bouldin, Ph.D.
Prof. of Electrical and Computer Engineering
419 Ferris Hall
1508 Middle Drive
University of Tennessee
Knoxville, TN 37996-2100
TEL: (865)-974-5444
FAX: (865)-974-5483
Email: dbouldin@tennessee.edu
http://www.eecs.utk.edu
http://www.eecs.utk.edu/people/faculty/emeritus/bouldin/
http://web.eecs.utk.edu/~bouldin/courses/651/overview.html

Custom Layout


Projects will NOT be submitted to MOSIS for fabrication since this is now being done in ECE 433. This course will present an introduction to the custom design of integrated circuits using computer-aided design software. Manual designs will be compared to those produced using automated methods. Nanometer scale design issues including crosstalk and power will be discussed.

Goals of ECE 651:

  • To understand the principles of hierarchical design of digital VLSI systems.

  • To utilize CAD tools to explore design alternatives and enhance productivity.

  • To experience the above goals through practical homework assignments implementing custom integrated circuits.


    What's New ?

    Accessing a Remote Host (Putty & Xming)

    Syllabus

    Students

    PROTECTED WEBSITE

    Our Text (Publisher)

    Website for Our Text

    Our CAD Tools Text (Publisher)

    Course Overview (pdf)

    Overview Slides (color pdf)

    Overview Slides (handout b/w pdf)

    Homework_1 - LOGIN, EMAIL and WEB PAGE

    Homework 2 -- Custom Cell Layout

    Homework_3 -- Designing an 8-bit Adder Datapath

    Homework 4 -- Loading Effects and Sizing Transistors

    Homework 5 -- Design, Verification and Installation of a Standard-height Cell

    Homework 6 -- Implementing a Macro

    Homework 7 -- Designing a Custom Analog Circuit

    Homework 8 -- Automatic Leafcell Generation

    Homework 9 -- Floorplanning and Clock Tree Synthesis

    Homework 10 -- Using Nanosim

    Homework 11 -- Signal Integrity and Crosstalk Analysis

    Homework Status

    Final Exam

    Handouts

    dbouldin@tennessee.edu