Restricted Website for ECE 652



ECE 652


Tasks for Spring 2007

Homework_1: Physical Synthesis (pchimaku)

Homework_2: Transaction Level Modeling (sbunch/mallen19)

Homework_3: EMC (jturnmir)

Homework_4: Implementing a LEON-based SoC (dbouldin)

HW4 notes: The tar file is now at: /usr/cad/course/soc.tar.gz
On page 15, before executing "make all", remove "*_inst.vhd" from the leon directory.
Take snapshots each time you use VSIM and record the number of standard-cell instances in the synthesized net-list.

hw4-errors-fixes-22jan07

Homework_4: Presentation (dbouldin)

Homework_5: PDA Optimization (jhatche2)

Homework_6: Learning SystemC (rchai)

Homework_7: Cocentric (dbouldin)

Homework_8: Seamless CVE/FPGA (pxi/jlee57)

Homework_9: Floorplanning with JupiterXT (vvenkata)

Homework_10: Platform Express (dbouldin)

Homework_11: Testing ASICs (ksundar1)

Homework_12: Mixed-Signal Simulation (scaylor)

Homework_13: Structured ASIC (dbouldin)

Homework_14: Signal Integrity (hkolli/rchannap)

Homework_15: skip

Homework_16: skip

Homework_17: Flash ADC (aanatonac/rgreenwe)



01-systemc-overview.pdf (64 slides; 0.7 MBytes)

02-systemc-tutorial.pdf (98 slides; 4.1 MBytes)

03-cocentric-dac00-slides.pdf (25 slides; 0.5 MBytes)

04-systemc-user-guide.pdf -- version 1.0 (210 pages; 1.0 MBytes)

05-systemc-funcspec20.pdf (135 pages; 0.3 MBytes)

06-systemc-overview20.pdf (13 pages; 0.1 MBytes)

07-systemc-userguide20.pdf -- version 2.0 (210 pages; 1.4 MBytes)

08-dw-directory-jan03.pdf (8 pages; 0.1 MBytes)

09-ip-showcase.pdf (1 page; 0.1 MBytes)

10-soc-test-slides.pdf (73 slides; 0.7 MBytes)

11-DW8051-datasheet.pdf (8 pages; 0.1 MBytes)

DW_8051 MacroCell:
/sw/synopsys/DW-8051-3.4a/DW8051_vhdl/
synopsys_tools, coreConsultant &
>  1) All the assembly tests provided with this version are compiled and
>  assembled with the latest as8051 assembler version 3.11.
>  2) Supports coreConsultant 3.2.3 and above.
>  3) FPGA Compiler-II synthesis is enabled in the coreConsultant flow
12-DW8051-databook.pdf (256 pages; 2.9 MBytes)

13-cocentric-datasheet.pdf (8 pages; 0.9 MBytes)

14-Platform Express User's Guide

PLATFORM EXPRESS: mentor_tools; px &; /sw/mentor/pxhome/doc/
15-Platform Express Component Integrator's Guide

16-systemc-fft

/sw/SystemC/systemc-2.0/examples/systemc/fft
17-systemc-rsa

/sw/SystemC/systemc-2.0/examples/systemc/rsa
18-cve-start.pdf

SEAMLESS CVE: mentor_tools; cve &; /sw/mentor/CVE4.3/cve_home.ss5/doc/pdfdoc
19-Block Matcher (a Seamless CVE tutorial)

20-transaction-level-modeling.pdf

21-Net Seminar on Reducing the SoC Design Cycle

22-rtl_systemc.pdf

23-Leon CPU core

24-ISVLSI_2003_Becker.pdf

25-Leon-Surrey.pdf

26-davis-eda.ppt

27-systemc.ppt

28-fdl01.pdf (Reusing VHDL modules in SystemC designs)

29-platform-design-date03.pdf

30-FPGA Core (pdf)

31-LEON.ppt

32-dw8051.ppt

33-audio-soc.pdf (105 pages)

34-Cocentric Tutorial (html)

35-SystemC Tutorial/HW (html)

36-AMBA_Bus_Hierarchy.ppt

37-amba-wrapper.txt

38-soc-design-slides-brodersen.pdf

39-flex-arch-design-brodersen.pdf

40--Final Report (html)

41--Open SoC Platform (html)

42--Volunteer SoC Platform (pdf)

43--Standard Cell Libraries for MOSIS (html)

44--AMI-06 StdCell Datasheets (html)

45--TSMC-0.18 StdCell Datasheets (html)

46--date04-open-soc (pdf)

The following files are under:
/sw/CDS/SOC23/tools/fe/gift/tutorial
47--first-encounter-workshoplab1.pdf

48--first-encounter-workshoplab2.pdf

49--first-encounter-workshoplab3.pdf

50--first-encounter-workshoplab4.pdf

51--Transaction-Level Modeling (pdf)

52--SoC Contest

53--SoC Thesis (pdf--Rishi)

54--SoC Thesis (ppt--Rishi)

55--Verifying IP (pdf)

56--synopsys-demographics.txt

57--tlm-matthews.pdf

58--cadence-tsmc-65nm.txt

59--chip-synthesis

60--amplify_issp_tutorial (pdf)

61--amplify_issp.tar.gz (design files)

62--Synopsys SNUG 2006 Tutorials

63--IBM Power5 Microprocessor (Hot Chips 2004)

64--low-power-intel.ppt

65--IBM eDRAM

66--Hafnium Chips

67--PPC405 User Manual (552 pages; 6.2 MBytes)

68--PPC405 Design View User Guide (54 pages; 1.2 MBytes)

69--PPC405 Design View Data Book (66 pages; 0.4 MBytes)

70--Design View Release Notes (12 pages; 0.2 MBytes)

71--Path Delay Testing Tutorial


dbouldin@utk.edu