Restricted Website for ECE 551
ECE 551
1a-overview-fpga-asic-color.pdf (1.5MByte)
1b-overview-fpga-asic-handout.pdf (0.6MByte)
2a-using-synthesis-color.pdf (0.7MByte)
2b-using-synthesis-handout.pdf (0.2MByte)
3a-hdl-examples-color.pdf (0.9MByte)
3b-hdl-examples-handout.pdf (0.2MByte)
4a-simulation-testing-color.pdf (0.9MByte)
4b-simulation-testing-handout.pdf (0.5MByte)
5a-place-and-route-color.pdf (0.5MByte)
5b-place-and-route-handout.pdf (0.2MByte)
6a-testing-asics-color.pdf (1.0MByte)
6b-testing-asics-handout.pdf (0.3MByte)
7a-reuse-color.pdf (1.4MByte)
7b-reuse-handout.pdf (1.1MByte)
8a-Overview Slides (71 color pages; 4.6MByte pdf)
8b-Overview Handout (12 b/w pages; 0.8MByte pdf)
9a-Design Flow Slides (31 color pages; 1.0MByte pdf)
9b-Design Flow Handout (7 b/w pages; 0.3MByte pdf)
10a-ASIC Testing Slides (32 color pages; 1.0MByte pdf)
10b-ASIC Testing Handout (6 b/w pages; 0.4MByte pdf)
10c-ASIC Testing Paper (15 b/w pages; 0.05MByte pdf)
11-Platform System-on-Chip Design
12-ASIC Trends
13a-Gomac Paper on Reconfigurable Systems (pdf)
13b-Gomac Slides on Reconfigurable Systems (pps)
14a-VHDL Examples Slides
14b-VHDL Examples Handout (8 pages; 2KByte pdf)
15-VirtexPro-Training (ppt)
16-VirtexII-Pro Example using PPC-405
44-Finite State Machine Coding in VHDL (pdf file)
45-Rapidchip Market (16 Kbytes pdf)
46-Rapidchip Overview (81 KBytes pdf)
47-Rapidchip Tutorial (818 KBytes pdf)
48-Interviewing at Intel
49-Guide to DSP Processors/Cores
50-Career Services
51-Circuit Sage
52-Pet Safe (Radio Fence)
53-ECE 551
54-Pilchard (pdf)
55-DesignWare Overview (pdf)
56-DesignWare Directory Listing (pdf)
57-DesignWare Directory Search (html)
58-DesignWare Example (DW02_mult) (pdf)
59-Designware Developer's Guide (pdf)
60-IP Protection (pdf)
61-IMEC IP (Wavelet) (pdf)
62-IMEC Reconfigurable Systems
63-Network on a Chip (pdf)
64-Using Synopsys to Test Designs (pdf)
65-Verification of Portable IP Blocks (pdf)
66-LFSR TestBench
67-Matrix Multiply (pdf)
68-AES Encryption on the Pilchard (pdf)
69-Block Level Incremental Synthesis and PAR
70-Design Flow
71-IBM Olympics Website Imputed Hits
72-IBM Olympics Website Page Views
73-IBM Olympics Website Visits
74-IBM Olympics Website Peak Hits
75-Wolf-ppt-slides (html)
76-Wolf-FPGA-Book
77-Brown-FPGA-Book
78-Sandige-FPGA-Book
79-Hamblen-FPGA-Book
80-Smith-FPGA-Book
81-aes-testing-core.pdf
82-tsmc-fab-jun04.pdf
83-eASIC-may04.pdf
84-design-for-yield-and-structured-asics.pdf
85-ip-china.pdf
86-soc-flow.pdf
87-Cost-Performance-Per-Watt
88-Design Skill Changes (xls)
89-xilinx-easy-path (pdf)
90-Failure-In-Time (FIT) rates for Myricom
91-Failure-In-Time (FIT) rates for Xilinx
92-Failure-In-Time (FIT) rates for Actel (pdf)
93-OpenCourseWare at MIT
94-hw6b-asserts (pdf)
95-timer-waves.jpg
96-timer-structure-coverage.jpg
97-timer-tester-missed-coverage.jpg
98-timer-control-fsm-missed-coverage.jpg
99-timer-asserts.jpg
100-timer-tutorial-highlights (7-page pdf)
101-timer-tutorial (242-page pdf)
102-hw6b-hdl2graphics (pdf)
103-create-new-project.jpg
104-project-content-import.jpg
105-hdl-import-vhdl.jpg
106-hdl-import-specify-files.jpg
107-hdl-import-target-convert.jpg
108-convert-hdl2graphics.jpg
109-log-conversion-complete.jpg
110-block-timer_tb.jpg
111-timer_tester-1.jpg
112-timer_tester-2.jp
113-timer_tester-3.jpg
114-block-timer.jpg
115-flow-control-fsm.jpg
116-flow-control-fsm-output.jpg
117-flow-control-fsm-nextstate-left.jpg
118-flow-control-fsm-nextstate-right.jpg
119-block-counter-struct.jpg
120-flow-bcdcounter.jpg
121-face-detection
122-Protocol-centric Verification (pdf)
123-stanford-stream-machine (pdf)
124-verification (jun 05)
125-NewCurricula05-v1 (pdf)
126-xilinx-shipments-aug05.txt
127-hdl-synth-slides (pdf)
128-hdl-synth-handout (pdf)
129-fixed-point math in C
130-Free Xilinx Book (pdf)
131-Synplify User Guide (pdf)
132-Verification Using Identify (pdf)
133-Intel Dual-Core (pdf)
134-551 Links
135-Altera High-Performance Computing (pdf)
136-IP-Patents (pdf)
137-Basics of Reconfigurable Computing
138-Mosterman Slides (pdf)
139-hds_des_exp_tut (36-page pdf)
140-hds_graphics2hdl (254-page pdf)
141-hds_hdl2graphics (42-page pdf)
142-IP-Encryption (html)
143-quickstart_synplify_pro (pdf)
144-quickstart_premier_altera (pdf)
145-quickstart_premier_xilinx (pdf)
146-synplicity-user-guide (pdf) (RAMS on p373)
147-Bluespec Synthesizable TestBench (pdf)
dbouldin@utk.edu